1. Field of the Invention
The present invention relates to an array substrate for a flat display device and a method for fabricating the same, more particularly, to an array substrate for a flat display device and a method for fabricating the same which can improve a performance and reliability.
2. Discussion of the Related Art
Following development of information oriented society, demands on display devices have been increased in variety of forms. In response to this, recently, various flat display devices have been studied, such as LCD (Liquid Crystal Display Device), PDP (Plasma Display Panel), ELD (Electro-Luminescent Display), VFD (Vacuum Fluorescent Display), and so on, some of which are utilized as display devices for various instruments, already.
Of above display devices, presently, the LCD is mostly used as mobile image display devices, while replacing the CRT (Cathode Ray Tube), owing to features and advantages of a good picture quality, light weight, thin, and low power consumption, and besides the use as the mobile image display devices, such as monitors of notebook computers, developing in variety of forms, such as TV sets which receive and display broadcasting signals, and monitors for computers.
A related art method for fabricating an array substrate for a flat display device will be described with reference to the attached drawings.
FIGS. 1A to 1F illustrate sections showing the steps of a related method for fabricating an array substrate for a flat display device.
Referring to FIG. 1A, a metal is deposited on a transparent insulating substrate 11, and subjected to photo and etching processes with a first mask to remove the metal selectively, to form a first gate electrode 12.
Then, a metal is deposited on an entire surface of the insulating substrate 11 including the first gate electrode 12, and subjected to photo and etching processes with a second mask to remove the metal selectively, to form a second gate electrode 13 on the first gate electrode 12 having a width greater than the first gate electrode 12.
Referring to FIG. 1B, a gate insulating film 14 is formed on an entire surface of the insulating substrate including the second gate electrode 13.
Then, an amorphous silicon layer is formed on the gate insulating film 14, and crystallized into a polysilicon layer.
Then, the polysilicon layer is subjected to photo and etching processes with a third mask to pattern the polysilicon layer selectively, to form an active layer 15 on the gate insulating film 14 over the first and second gate electrodes 12 and 13.
Referring to FIG. 1C, an etch stopper layer 16 is formed on an entire surface of the insulating substrate 11 including the active layer 15, and subjected to photo and etching processes with a fourth mask to pattern the etch stopper layer 16 to leave a predetermined portion of the etch stopper layer 16 on the active layer 15. In this instance, the etch stopper layer 16 is patterned such that the etch stopper layer 16 has an area smaller than the second gate electrode 13.
In this instance, the etch stopper layer 16 is formed for preventing the underlying active layer 15 from being etched at the time source/drain electrodes are formed.
Referring to FIG. 1D, an n+ doped amorphous silicon layer 17 is formed on an entire surface of the insulating substrate 11 including the etch stopper layer 16.
Then, a metal is deposited on the amorphous silicon layer 17, and subjected to photo and etching processes with a fifth mask to remove the metal selectively, to form a source electrode 18a and a drain electrode 18b. 
Then, the amorphous silicon layer 17 exposed by the source electrode 18a and the drain electrode 18b is removed selectively. In this instance, the source electrode 18a and the drain electrode 18b are formed spaced a predetermined distance from each other for forming a channel later.
Referring to FIG. 1E, a planarizing layer 19 is formed on an entire surface of the insulating substrate 11 including the source electrode 18a and the drain electrode 18b, and subjected to photo and etching processes with a sixth mask to remove the planarizing layer 19 selectively to expose a predetermined portion of a surface of the drain electrode 18b, to form a contact hole 20 therein.
Referring to FIG. 1F, ITO is deposited on an entire surface of the insulating substrate 11 including the contact hole 20, and subjected to photo and etching processes with a seventh mask to remove the ITO selectively to form a pixel electrode 21 connected to the drain electrode 18b, electrically.
However, the related art method for fabricating an array substrate for a flat display device has the following problems.
The use of structures of the etch stopper layer and the double gates causes to increase a number of masking processes, which increases a cost.